CAPE Physics Unit 2 · 2007 · Paper 2 · Question 7(b)(ii)

Figure 8 shows three T-type flip-flops connected in series, triggering on negative-going input edges (logic 1 to logic 0 transition).

Copy and complete Table 4 showing the logic states at outputs X, Y, and Z for clock pulses 0 through 4, given all outputs start at zero.

This question uses a figure or table from the paper — you'll see it when you practise.