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4 marksComputer Architecture

CAPE Computer Science Unit 1 · 2013 · Paper 2 · Question 1(a)(ii)

Questions on computer architecture, data representation, and logic design.

Four lines, l0, l1, l2, l3, are connected to the input lines of a 4 to 1 line multiplexer. Explain how the multiplexer can send the signal in l1 as output for one second followed by the signal in l3.

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Other parts of this question

  1. 1(a)(i)Draw a clearly labelled block diagram of a 4 to 1 line multiplexer.[4 marks]
  2. 1(a)(iii)Give TWO properties of a flip-flop and state ONE use of this device.[3 marks]
  3. 1(b)(i)Find the 4-bit signed magnitude representation of –5.[2 marks]
  4. 1(b)(ii)Find the 4-bit one's complement representation of –5.[1 mark]
  5. 1(b)(iii)Find the 4-bit two's complement representation of –5.[2 marks]
  6. 1(c)A system represents decimal numbers using sign (S), mantissa (M) and exponent (E) with 1 bit for sign, 3 bits for exponent, and 4 bits for mantissa. Determine…[3 marks]
  7. 1(d)(i)Draw the truth table for a NOT gate.[2 marks]
  8. 1(d)(ii)Draw the truth table for an AND gate.[2 marks]
  9. 1(d)(iii)Draw the truth table for an OR gate.[2 marks]

More practice: the rest of this paper · more Computer Architecture questions · all CAPE Computer Science Unit 1 past papers